发明名称 BUS COLLATION CIRCUIT
摘要 PROBLEM TO BE SOLVED: To effectively prevent the occurrence of malfunction by an alternate signal outputted from an internal clock or the like of an LSI. SOLUTION: A bus collation circuit having a two-line type inspection circuit for respectively inputting two pieces of I/O information from two synchronously driven CPUs and mutually comparing the I/O information pair and an error display circuit for outputting an alternate signal when the contents of the compared I/O information pair coincide with each other, or stopping the output of the alternate signal when non-coincidence of the I/O information pair is detected is provided with a substitution means for respectively substituting M series codes for the two pieces of I/O information respectively inputted to the two-line type inspection circuit, an extraction means for extracting the M series codes from the output signal of the error display circuit and a decision means for deciding the coincidence of two pieces of I/O information at the time of extracting the M series codes and deciding the non-coincidence when the M series codes are not extracted.
申请公布号 JP2002247012(A) 申请公布日期 2002.08.30
申请号 JP20010038747 申请日期 2001.02.15
申请人 NIPPON SIGNAL CO LTD:THE 发明人 NAKAMURA HIDEO;TAIRA MUNEHISA;KAJIWARA TOSHIHIKO
分类号 H04L1/00;(IPC1-7):H04L1/00 主分类号 H04L1/00
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