发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To reject and relieve a defective bit caused by abnormality of bit line voltage by making bit line voltage variable and accelerating defect of a bit. SOLUTION: This circuit is provided with a VBL generating circuit 100, a test mode discriminating circuit 200, a large pump 300, a small pump 400. Thereby, defect of a bit having no margin can be detected for pre-charge voltage of a higher bit line or a lower bit line by making pre-charge voltage of bit lines variable.
申请公布号 JP2002245797(A) 申请公布日期 2002.08.30
申请号 JP20010040172 申请日期 2001.02.16
申请人 MITSUBISHI ELECTRIC CORP 发明人 ITO KANJI;KITADE OSAMU
分类号 G01R31/28;G11C11/401;G11C11/4074;G11C29/00;G11C29/02;G11C29/50;(IPC1-7):G11C29/00 主分类号 G01R31/28
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