| 摘要 |
PROBLEM TO BE SOLVED: To shorten the time when low priority access occupies to make high priority access wait and reduce the number of steps of a FIFO buffer in each access system by a comparatively simple circuit configuration. SOLUTION: A timing generation part 17 for generating a sample/hold control signal indicating possible timing/impossible timing of mediation is provided, and next time operation mode is determined based on operation mode at the time of preceding access, the results of line address coincidence detection, and the results of read/write switching detection to generate access timing and the sample/hold control signal in the timing generation part 17. Access mediation is performed per access cycle in accordance with the sample/hold control signal generated by the timing generation part 17 to control an address counter and a data path in a peripheral circuit constituting a plurality of access systems in an arbiter part 16.
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