发明名称 |
Die testing using top surface test pads |
摘要 |
Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding test pads on the top surface of the die. The added test pads allow a tester to probe and test more circuits within the die simultaneously. Also, the added test pads contribute to a reduction in the amount of test wiring overhead traditionally required to access and test circuits within a die, thus reducing die size.
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申请公布号 |
US2002119650(A1) |
申请公布日期 |
2002.08.29 |
申请号 |
US20020051536 |
申请日期 |
2002.01.18 |
申请人 |
WHETSEL LEE D.;ANTLEY RICHARD L. |
发明人 |
WHETSEL LEE D.;ANTLEY RICHARD L. |
分类号 |
H01L23/58;(IPC1-7):H01L21/44 |
主分类号 |
H01L23/58 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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