发明名称 |
Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test |
摘要 |
A method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain has a plurality of scan cells. The method and apparatus allows generating and loading N pseudorandom or predetermined stimuli to all the scan cells within the N clock domains in the integrated circuit or circuit assembly during the shift operation, applying an ordered sequence of capture clocks to all the scan cells within the N clock domains during the capture operation, compacting or comparing N output responses of all the scan cells for analysis during the compact/compare operation, and repeating the above process until a predetermined limiting criteria is reached. A computer-aided design (CAD) system is further developed to realize the method and synthesize the apparatus.
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申请公布号 |
US2002120896(A1) |
申请公布日期 |
2002.08.29 |
申请号 |
US20020067372 |
申请日期 |
2002.02.07 |
申请人 |
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发明人 |
WANG LAUNG-TERNG;HSU PO-CHING;KAO SHIH-CHIA;LIN MENG-CHYI;WANG HSIN-PO;CHAO HAO-JAN;WEN XIAOQING |
分类号 |
G01R31/28;G01R31/317;G01R31/3185;G06F17/50;H01L21/82;H01L21/822;H01L27/04;(IPC1-7):G01R31/28 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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