发明名称 |
Memory circuit redundancy control |
摘要 |
A memory having flexible column redundancy and flexible row redundancy comprises a multi-column stick configuration each column stick comprising a plurality of data lines. Further, the memory has a multi-row stick configuration, with each row stick comprising a plurality of data rows. Positioned on either side of the memory are redundant column sticks each comprising a plurality of data lines. Positioned above and below the memory are redundant row sticks, each comprising a plurality of data rows. A column redundancy control identifies a faulty operating column stick in the memory and generates a column shift control signal to a column shift multiplexer that responds to the column shift control signal to substitute in the memory a redundant column stick for the identified faulty operating column stick. Further, the memory comprises a row redundancy controller identifies a faulty operating row stick in the memory to generate a row shift control signal to a row shift multiplexer. The row shift multiplexer responds to the row shift control signal to substitute in the memory a redundant row stick for the identified faulty operating row stick in the memory.
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申请公布号 |
US2002118581(A1) |
申请公布日期 |
2002.08.29 |
申请号 |
US20020077432 |
申请日期 |
2002.02.15 |
申请人 |
PITTS ROBERT L.;TIMMONS CLAYTON O. |
发明人 |
PITTS ROBERT L.;TIMMONS CLAYTON O. |
分类号 |
G11C29/00;(IPC1-7):G11C29/00 |
主分类号 |
G11C29/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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