REDUCTION OF METAL SILICIDE/SILICON INTERFACE ROUGHNESS BY DOPANT IMPLANTATION PROCESSING

摘要

Deleterious roughness of interfaces (143) between metal silicide layers (142) and doped Si regions (200, 202) arising during conventional silicide processing for forming shallow-depth source and drain junction regions (204, 206) of MOS transistors and/or CMOS devices due to poor compatibility of particular dopants and metal silicides is avoided, or at least substantially reduced, by implanting a first (main) dopant species having relatively good compatibility with the metal silicide, such that the maximum concentration thereof is at a depth above the depth to which silicidation reaction occurs and implanting a second (auxiliary) dopant species having relatively poor compatibility with the metal silicide, wherein the maximum concentration thereof is less that that of the first (main) dopant and is at a depth below the depth to which silicidation reaction occurs. The invention enjoys particular utility is forming NiSi layers on As-doped Si substrates.