| 摘要 |
The integrated DRAM memory module has sense amplifiers which are each formed, in the integrated module, from a multiplicity of transistor structures that are arranged regularly in cell arrays and include amplification transistors for bit line signal amplification. The amplification transistors lie opposite one another in pairs, are structurally identical, and are arranged equally spaced apart in rows. Voltage equalization transistors ensure voltage equalization between sense amplifier drive signals. The cell array order provides for each row with amplification transistors situated in a structurally identical transistor environment to be interrupted in a predetermined period by voltage equalization transistors. The structure of the voltage equalization transistors in a region of proximity to the adjoining amplification transistors is adapted to the structure thereof, and the voltage equalization transistors are at the same distance from the mutually adjoining amplification transistors as the amplification transistors of the same row are from one another.
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