| 摘要 |
A phase locked loop (PLL) circuit is provided having a DC biasing circuit (40, 42A, 42B) that enables the PLL to operate with a single power supply voltage, and which also eliminates the dead hone associated with the phase detector (14) of the PLL. The PLL includes a phase detector for detecting the phase difference between a reference clock signal (12) and a feedback signal (38) and for generating phase pulse outputs corresponding to this phase difference, an integrator (18, 20, 22, 24, 26, 28, 30) coupled to the phase pulse outputs for generating a phase voltage in proportion to the pulse width of the phase pulse outputs, and a voltage controlled oscillator (32) coupled to the phase voltage for generating a local oscillator signal that is synchronized to the reference clock signal and which is coupled to the feedback signal (44). The DC biasing circuit generates a variable pulse width bias signal that is merged with the phase pulse outputs in order to polarize the integrator inputs at a particular DC bias level. In a first embodiment, the DC biasing circuit merges the variable pulse width bias signal with both positive and negative phase outputs from the phase detector in order to polarize the integrator. In a second embodiment, the DC biasing circuit merges the variable pulse width bias signal with only one of the positive or the negative phase outputs from the phase detector in order to simultaneously polarize the integrator and to eliminate the dead zone associated with the phase detector by injecting a continuous phase error into the PLL feedback signal. |
