| 摘要 |
PROBLEM TO BE SOLVED: To provide a new method and a device for reducing the complicity and hardware of an IC tester and simultaneously reducing test circuit overhead in an integrated circuit without sacrificing DFT and BIST functions. SOLUTION: The integrated circuit includes a test access port(TAP) and a DFT scan circuit. The TAP includes in its TAP block a linear feedback shift, register, a signature register with a plurality of inputs, a step counter, a shift counter, a step/shift controller, an MISR mask register, etc., and is capable of automatically creating BIST test patterns through the use of a TAP circuit and simultaneously loading them to a plurality of parallel scan paths over a whole digital circuit. |
