发明名称 Apparatus and method for power continuity testing in a parallel testing system
摘要 Multiple devices can be tested simultaneously for power continuity or for other power performance characteristic(s). If any of the devices have short circuit defects, for example, the fuse devices connected between these defective devices and a single power supply restrict the amount of current drawn by the defective devices. This allows power continuity testing to continue for all of the other devices. At the same time, the reduced voltage level of the defective devices, caused by the restriction of current by their corresponding fuse device, can be detected by the voltage measurement device. The reduced voltage levels allow the defective devices to be identified by a test control apparatus and to be excluded from subsequent testing.
申请公布号 US6441637(B1) 申请公布日期 2002.08.27
申请号 US20000670254 申请日期 2000.09.26
申请人 INTEL CORPORATION 发明人 NEEB JAMES E.
分类号 G01R31/28;G01R31/30;H02M1/00;H02M1/32;H02M3/335;(IPC1-7):G01R31/26 主分类号 G01R31/28
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