| 摘要 |
A low power linear feedback shift register includes an ordered set of register steps including memory devices. Enabling devices enable a single current memory device at every shift operation. Each register step includes a lower power memory device consuming a minimum amount of power when disabled, and a feedback device, an output terminal thereof being connected to an input terminal of the memory device, the feedback device having first and second input terminals connected to an output terminal of the memory device and an output terminal of a second subsequent memory device, respectively, in the set. The output terminal of each memory device is connected to a selection device, selecting at every shift operation the output terminal of a first subsequent memory device following the current memory device being enabled at the current shift operation.
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