发明名称 Method of measuring combined critical dimension and overlay in single step
摘要 A semiconductor wafer structure in a overlay pattern that permits determination of overlay and critical dimension features by CD SEM in a single pass along a given axis, comprising:a) a center feature section that provides a critical dimension point along a given axis;b) plurality of smaller sections positioned adjacent to the center feature section along the given axis that include a plurality of spaces between each of the plurality of smaller sections; andc) a plurality of displacement lines adjacent to the plurality of the smaller sections to displace a plurality of spaces.
申请公布号 US6440759(B1) 申请公布日期 2002.08.27
申请号 US20010893475 申请日期 2001.06.29
申请人 INFINEON TECHNOLOGIES AG 发明人 COMMONS MARTIN;MONO TOBIAS;KLEE VELT;POHL JOHN;WENSLEY PAUL
分类号 G03F7/20;H01L23/544;(IPC1-7):H01L21/00 主分类号 G03F7/20
代理机构 代理人
主权项
地址