发明名称 |
Frequency-doubling delay locked loop |
摘要 |
A frequency multiplier circuit comprising a delay line receiving at one end thereof a reference clock for generating clock tap outputs from respective ones of a plurality of period matched delay elements; a clock combining circuit responsive to pairs of tap outputs for generating a rising and falling edge of an output clock pulse from respective ones of the pairs whereby the output clock period is less than the input clock period. |
申请公布号 |
US6441659(B1) |
申请公布日期 |
2002.08.27 |
申请号 |
US20000562024 |
申请日期 |
2000.05.01 |
申请人 |
MOSAID TECHNOLOGIES INCORPORATED |
发明人 |
DEMONE PAUL W. |
分类号 |
G11C11/407;G06F1/08;H03K5/00;H03K5/15;H03L7/07;H03L7/08;H03L7/081;H03L7/16;(IPC1-7):H03L7/06 |
主分类号 |
G11C11/407 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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