发明名称 Circuit arrangement for generating the control potential for a field-effect transistor
摘要 An explanation is given of a circuit arrangement for generating the control potential for a field-effect transistor from the output voltage (VA) of a filter circuit (20). In order to reduce the noise component thereof, the output terminal (A) of the filter circuit (20) is connected to a capacitive voltage divider (C1, C2), the tap of which carries the control potential. It is possible to control the charge state of the voltage divider (C1, C2) for the purpose of setting a predetermined potential value at the tap (10).
申请公布号 US6441672(B1) 申请公布日期 2002.08.27
申请号 US20000517216 申请日期 2000.03.02
申请人 MICRONAS GMBH 发明人 ULRICH THEUS
分类号 H03L7/093;(IPC1-7):H03K17/16 主分类号 H03L7/093
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