Overcoming finite amplifier gain in a pipelined analog to digital converter

摘要

An apparatus for correcting for the finite gain of an amplifier assembly in a pipelined analog to digital converter (ADC) is disclosed in which an input signal to an amplifier module of one stage of the pipelined ADC is sampled and provided to the input of an amplifier of a subsequent stage as a feed-forward error correction signal. The feed-forward correction signal is subtracted in the next stage from the output residue signal of the previous stage input to the second subsequent stage amplifier in order to remove part of the output signal from the first stage that includes the finite gain of the amplifier.