| 摘要 |
An apparatus is presented for expediting the execution of address-dependent micro instructions in a pipeline microprocessor having design characteristics-complexity, power, and timing-that are not significantly impacted by the number of stages in the microprocessor's pipeline. The present invention provides a cache for storage of multiple intermediate address operands. The cache is accessed by an address-dependent micro instruction to retrieve a required address operand. The apparatus includes an update forwarding cache, address update logic, and address operand configuration logic. The update forwarding cache stores the intermediate address operands. The address update logic receives the intermediate address operands as they are generated and enters the intermediate address operands into the update forwarding cache. The address operand configuration logic accesses the intermediate address operands to configure and provide an address operand that is required an address-dependent micro instruction.
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