Radiation-hard silicon cryo-CMOS process suitable for charge-coupled devices, and a device made according to this process

摘要

A silicon-based radiation-hard cryo-CMOS CCD process suitable for fabrication of devices (100) with sub-micron feature sizes. A re-oxidized nitride/oxide (RONO) layer (49'') is preserved in the CCD area (32) while plasma etching is used to define polysilicon 1 gates (50') in the active FET area of the device. Thereafter, a wet chemical etching process, which does not destroy the integrity of the RONO layer (49'') in the CCD area, is carried out. A channel stop (48) is formed after the field oxidation step in the active FET area to reduce the space required for minimum diode breakdown voltage between the n+ source/drain region and the p+ channel stop.