| 摘要 |
PROBLEM TO BE SOLVED: To realize a memory control circuit allowing a transmitter-receiver to realize the reduction of a chip size, cost and power consumption by reducing the number of memories. SOLUTION: This memory control circuit is provided with a monitoring circuit 110 for monitoring an access demand signal CWE corresponding to an access demand to an RAM 101 from a CPU, and an access demand signal ERE corresponding to an access demand to an RAM 101 from an external device, and a control circuit (an OR gate 107, an AND gate 108, and a NOR gate 109) for scheduling to validate the access demand signal ERE after giving priority to the access demand signal CWE of high priority.
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