发明名称 SCHEDULING METHOD AND APPARATUS THEREFOR
摘要 <p>PROBLEM TO BE SOLVED: To provide a scheduling method and an apparatus therefor which realizes the reduction of the scheduling process time and an impartial scheduling process. SOLUTION: The apparatus has a plurality of processing orders different in scheduling object among a plurality of input circuits. According to the processing order that a top priority output circuit of a top priority input circuit is processed at a first priority, scheduling processes of all the input circuits are executed in parallel and the top priority input circuit, and a top priority output circuit of each input circuit are updated every scheduling cycle, thereby always determining a top priority output circuit in own input circuits when each input circuit becomes a top priority circuit. With respect to a single input circuit, an output circuit in the input circuit is equally selected to make possible an impartial scheduling, even if the order is nearly fixed among the input circuits, and, on the other hand, the process time is reduced owing to the parallel processing to make also possible a high speed scheduling.</p>
申请公布号 JP2002237839(A) 申请公布日期 2002.08.23
申请号 JP20010034339 申请日期 2001.02.09
申请人 FUJITSU LTD 发明人 MATSUOKA NAOKI;TOMONAGA HIROSHI;KAWARAI KENICHI;NAGATA MASAKATSU
分类号 H04L12/815;H04L12/863;H04L12/865;H04L12/867;(IPC1-7):H04L12/56 主分类号 H04L12/815
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