发明名称 |
Level shift circuit and semiconductor device using the same |
摘要 |
A first and second circuits are connected in parallel between a first supply line supplying a first potential and a second supply line supplying a second potential. Each of the first and second circuits has first and second P-type transistors and an N-type transistor connected in series in order from the first-supply-line side. The gate of the first P-type transistor in the first circuit is connected to the drain of the N-type transistor in the second circuit. The gate of the first P-type transistor in the second circuit is connected to the drain of the N-type transistor in the first circuit. Input potentials opposite to each other are applied to the gates of the N-type transistors in the first and second circuits respectively and output potentials level-shifted from the input potentials are output from the drains of the N-type transistors in the first and second circuits respectively. A third supply line supplying a third potential between the first and second potentials is connected to the gate of the second P-type transistor in each of the first and second circuits.
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申请公布号 |
US2002113769(A1) |
申请公布日期 |
2002.08.22 |
申请号 |
US20010930884 |
申请日期 |
2001.08.14 |
申请人 |
TSUCHIYA MASAHIKO |
发明人 |
TSUCHIYA MASAHIKO |
分类号 |
G09G3/36;G09G3/20;H01L21/822;H01L27/04;H03K3/356;H03K17/10;H03K19/0185;(IPC1-7):H03K19/017;G05F1/10 |
主分类号 |
G09G3/36 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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