| 摘要 |
<p>A semiconductor integrated circuit for realizing a receiving circuit for stably determining the value of a symbol even if the phase of received serial-transmission data shifts from that of a sampling clock signal or even if the waveform of received serial-transmission data degrades because of uneven delay of a signal on a transmission line when serial-transmission data is received. The semiconductor integrated circuit comprises a first clock signal generator circuit for generating clock signals of N phases synchronized with an input clock signal, a second clock signal generator circuit for generating clock signals of M phases (M ≠ N) synchronized with a selected one of the clock signals of N phases generated by the first clock signal generator circuit, and a calculation circuit for calculating the control value used for selecting one of the clock signals of N phases on the basis of the logic value of the serial-transmission data sampled by using the clock signals of N phases and those of M phases.</p> |
