Power saving semi-conductor integrated circuit

摘要

In order to provide a reduction in power wasted by leakage currents in a CMOS SRAM without unduly compromising speed performance or increasing the chance of data errors, the invention proposes a device and method for selectively deactivating peripheral parts of the memory when the memory is in a stand-by mode. The device proposed for implementing the invention comprises a memory made up of cells (10) and peripheral circuits (20), and a transistor switch (30A-30I) capable of interrupting the power supply to the peripheral circuits (20) depending on the voltage supplied to it on a power down (PD) select line and thus reducing the power wasted by leakage currents in the peripheral circuits (20). The transistor switch (30A-30I) cooperates with the peripheral circuits (20) to ensure that data integrity is maintained in a stand-by mode and that a high operating speed is possible when either writing to or reading from the memory cells (10). Preferably, the transistor switch is distributed along the exterior of the peripheral circuits.