ADDRESS BUFFER CIRCUIT FOR ASYNCHRONOUS SDRAM

摘要

PURPOSE: An address buffer circuit for asynchronous SDRAM(Synchronous Dynamic Random Access Memory) is provided to prevent an address multi selection by controlling a width of an ATD(Address Transition Detection) pulse and securing an AC(Activation and Counter-activation) margin inter selection signal. CONSTITUTION: A first delay circuit includes a plurality of delay circuits for outputting a first signal(A) which has the same phase of an input address(ADDR). A second delay circuit includes a plurality of delay circuits for outputting a second signal(AB) which has an inverse-phase of the address(ADDR). A clock generation circuit(25) generates a first clock(ATD) in response to the signal which has the phase of the address(ADDR) and the signal which has the same phase opposite to the address(ADDR). The first signal(A) and the second signal(AB) perform a logic transition respectively in a first state of the first clock(ATD).