LATCHING SERIAL DATA IN AN INK JET PRINT HEAD

摘要

A print data loading circuit receives N bits of serial data on a serial input data line (SD), and provides the input data to a data bus in an addressing circuit (30) for addressing one or more image-forming elements in a printing device. The data loading circuit includes an N-bit serial shift register (14) having N number of serially-coupled sigle-bit storage registers. The data loading circuit also includes N-1 number of data latches (L1-Ln-1), each having a data input coupled to a data output of a corresponding one of the single-bit storage registers (R1-Rn). The data outputs of the data latches are coupled to N-1 number of selection lines (P1-Pn-1) that are coupled to the data bus. Each data latch has a clock input (CL) that is coupled to the data output of the Nth storage register (Rn). Based on this configuration, a bit provided at the Nth-register data output Rn) acts as a load trigger bit to cause the other data bits in the other single-bit storage registers to be loaded into the N-1 number of date latches(L1-Ln-1). By providing the trigger bit from the Nth register of the shift register, the present invention eliminates the need for a second clock input to latch the print data latches. Eliminating a second clock input reduces print head costs and potential Eh1I problems.