发明名称 Method and apparatus for computer system reliability
摘要 According to one embodiment, a multiprocessing system includes a first processor, a second processor, and compare logic. The first processor is operable to compute first results responsive to instructions, the second processor is operable to compute second results responsive to the instructions, and the compare logic is operable to check at checkpoints for matching of the results. Each of the processors has a first register for storing one of the processor's results, and the register has a stack of shadow registers. The processor is operable to shift a current one of the processor's results from the first register into the top shadow register, so that an earlier one of the processor's results can be restored from one of the shadow registers to the first register responsive to the compare logic determining that the first and second results mismatch. It is advantageous that the shadow register stack is closely coupled to its corresponding register, which provides for fast restoration of results. In a further aspect of an embodiment, each processor has a signature generator and a signature storage unit. The signature generator and storage units are operable to cooperatively compute a cumulative signature for a sequence of the processor's results, and the processor is operable to store the cumulative signature in the signature storage unit pending the match or mismatch determination by the compare logic. The checking for matching of the results includes the compare logic comparing the cumulative signatures of each respective processor. It is faster, and therefore advantageous, to check respective cumulative signatures at intervals rather than to check each individual result.
申请公布号 US2002116662(A1) 申请公布日期 2002.08.22
申请号 US20010791143 申请日期 2001.02.22
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 HOFSTEE HARM PETER;NAIR RAVI
分类号 G06F11/18;G06F9/30;G06F9/38;G06F11/14;G06F11/16;(IPC1-7):H04L1/22 主分类号 G06F11/18
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