发明名称 |
Phase alignment of data to clock |
摘要 |
A phase alignment circuit in a serial transmitter aligns a parallel input data stream to a first transmission clock before conversion to a serial output data stream using a second transmission clock which is a multiple of the first transmission clock. The phase alignment circuit introduces less delay, i.e., the output of the phase alignment circuit lags the input of the phase alignment by a few number of clock cycles (e.g., less than 2 clock cycles). The phase alignment circuit demultiplexes the input data stream into a plurality of intermediate data streams using a plurality of multi-phase clocks referenced to a data clock and multiplexes the plurality of intermediate data streams using sequence signals referenced to the first transmission clock. The sequence signals are initialized according to a reset condition and at least one of the multi-phase clocks.
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申请公布号 |
US2002114416(A1) |
申请公布日期 |
2002.08.22 |
申请号 |
US20010873750 |
申请日期 |
2001.06.04 |
申请人 |
ENAM SYED K.;DJAFARI MASOUD;KE BO-SHIOU |
发明人 |
ENAM SYED K.;DJAFARI MASOUD;KE BO-SHIOU |
分类号 |
H03D7/14;H03H11/52;H03K19/018;H03L7/085;H03L7/087;H03L7/089;H03L7/091;H03L7/099;H03L7/10;H03L7/14;H03L7/18;H04J3/06;H04L1/24;H04L7/00;H04L7/033;H04L25/02;H04L25/05;(IPC1-7):H03D3/24 |
主分类号 |
H03D7/14 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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