PLL HAVING FAST FREQUENCY LOCK CONTROL CIRCUIT AND METHOD FOR REDUCING FREQUENCY LOCK TIME OF THE SAME

摘要

PURPOSE: A PLL(Phase Locked Loop) having a fast frequency lock control circuit and a method for reducing a frequency lock time of the same are provided to reduce a frequency lock time and improve characteristics of the PLL. CONSTITUTION: A phase detector(21) compares a reference clock signal(fr) with a feedback clock signal(fv) and detects a phase difference. A fast frequency lock control circuit(23) disconnects the phase detector(21) from a loop filter(25). The fast frequency lock control circuit(23) provides static current to a loop filter(25) during a predetermined time. The fast frequency lock control circuit(23) connects the phase detector(21) with the loop filter(25) after providing the static current to a loop filter(25) during a predetermined time. A voltage controlled oscillator(27) generates an output clock signal(fo) and changes frequencies of the output clock signal(fo) in response to an output voltage of the loop filter(25). A demultiplier(29) demultiplies the output clock signal(fo) and provides the demultiplied signal as the feedback clock signal(fv).