SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE CAPABLE OF SELF-ANALYZING REDUNDANCY REPLACEMENT ADAPTING TO CAPACITIES OF PLURAL MEMORY CIRCUITS INTEGRATED THEREIN

摘要

PURPOSE: A semiconductor integrated circuit device capable of self-analyzing redundancy replacement adapting to capacities of plural memory circuits integrated therein is provided to flexibly adapt to not only a case where a change occurs in memory capacity of a DRAM core but a case where a change also occurs in the number of redundant memory cell rows. CONSTITUTION: The semiconductor integrated circuit(1000) includes n DRAM cores(100.1-100.n) and logic circuits(200.1-200.n) for performing data supplying/receiving to/from DRAM cores(100.1-100.n) to perform a logic operation. The semiconductor integrated circuit(1000) further includes a built-in self-test circuit(300) for performing a built-in self-test on each of DRAM cores(100.1-100.n) and a built-in redundancy analysis circuit(400) for analyzing and determining what redundancy saving is performed on a defective bit detected in each of the DRAM cores(100.1-100.n) based on a test result in built-in self-test circuit(300), wherein the analysis for redundancy saving unit, in each of the DRAM cores, a normal memory cell row and a normal cell column in each of which a defective bit exists are replaced with plural redundancy memory rows and plural redundancy columns in order to save the normal memory cell row and the normal cell column.