发明名称 Test interconnect for semiconductor components having bumped and planar contacts
摘要 An interconnect for testing semiconductor components having both bumped contacts, and planar contacts, is provided. The interconnect includes: a substrate, first contacts on the substrate for electrically engaging the bumped contacts, and second contacts on the substrate for electrically engaging the planar contacts. In illustrative embodiments the first contacts include recesses in the substrate covered with a conductive layer, or recesses formed in a compliant layer on the substrate, or conductive polymer donuts sized and shaped to retain the bumped contacts. In illustrative embodiments the second contacts include etched pillars having penetrating projections, or conductive polymer bumps having penetrating particles, or flat topped projections having a compliant layer thereon. The interconnect can be used to construct a die level test carrier for testing components in singulated form, or to construct a wafer level test carrier for testing components in wafer or panel form.
申请公布号 US6437451(B2) 申请公布日期 2002.08.20
申请号 US20000738915 申请日期 2000.12.14
申请人 MICRON TECHNOLOGY, INC. 发明人 FARNWORTH WARREN M.;AKRAM SALMAN
分类号 G01R1/04;G01R1/067;G01R1/073;H05K1/11;H05K3/32;(IPC1-7):H01L23/48;H01L23/52;H01L29/40 主分类号 G01R1/04
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