| 摘要 |
A method and apparatus are described for decoding a stream of data which has been encoded into a chip stream so that a chip rate and phase of the chip stream can be derived from the encoded data. The method comprises the steps of: generating a clock signal (clk) having a clock rate which is approximately equal to the chip rate or an integer multiple thereof; passing the chip stream along a multi-stage delay line (14); for each clock cycle, sampling data of the chip stream at a plurality of the stages of the delay line to produce a set of oversamples (oversamples); for each clock cycle, producing an estimate (edgepos) of a position in a respective set of the oversamples of a chip edge in the chip stream; for at least some of the clock cycles, selecting at least one of the oversamples (dec13 chip(0), dec_chip(1)) having a position within a confined range with respect to the estimated chip edge position; and outputting the selected oversamples. The method obviates the need for a high frequency oversampling clock or a variable frequency clock. The delay per stage of the delay line does not need to be stabilised if a calibration method is employed periodically between reception sessions.
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