发明名称 PD-SOI substrate with suppressed floating body effect and method for its fabrication
摘要 A partially-depleted Silicon-on-Insulator (SOI) substrate with minimal charge build up and suppressed floating body effect is disclosed, as well as a simple method for its fabrication. A thin Si/Ge epitaxial layer is grown between two adjacent epitaxial silicon layers of a SOI substrate, and as part of the silicon epitaxial growth. The thin Si/Ge epitaxial layer introduces misfit dislocations at the interface between the thin Si/Ge epitaxial layer and the adjacent epitaxial silicon layers, which removes undesired charge build up within the substrate.
申请公布号 US6437375(B1) 申请公布日期 2002.08.20
申请号 US20000587190 申请日期 2000.06.05
申请人 MICRON TECHNOLOGY, INC. 发明人 BEAMAN KEVIN L.
分类号 H01L27/12;H01L29/786;(IPC1-7):H01L31/072;H01L31/109;H01L31/032;H01L31/033 主分类号 H01L27/12
代理机构 代理人
主权项
地址
您可能感兴趣的专利