发明名称 Method of forming crown-type MIM capacitor integrated with the CU damascene process
摘要 A method for fabricating an increased capacitance metal-insulator-metal capacitor using an integrated copper damascene process is described. A contact node is provided overlying a semiconductor substrate. An intermetal dielectric layer is deposited overlying the contact node. A damascene opening is formed through the intermetal dielectric layer to the contact node. A first metal layer is formed on the bottom and sidewalls of the damascene opening and overlying the intermetal dielectric layer. A first barrier metal layer is is deposited overlying the first metal layer. A dielectric layer is dpeosited overlying the first barrier metal layer. A second barrier metal layer is deposited overlying the dielectric layer. A second metal layer is formed overlying the second barrier metal layer and completely filling the damascene opening. The layers are polished back to leave the first metal layer, the dielectric layer, the first and second barrier metal layers, and the second metal layer only within the damascene opening wherein the first metal layer forms a bottom electrode, the dielectric layer forms a capacitor dielectric, and the second metal layer forms a top electrode to complete fabrication of a crown-type capacitor in the fabrication of an integrated circuit device.
申请公布号 US6436787(B1) 申请公布日期 2002.08.20
申请号 US20010912735 申请日期 2001.07.26
申请人 TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY 发明人 SHIH WONG-CHENG;LEE TZYH-CHEANG;TING WENCHI;LIN CHIH-HSIEN;WONG SHYH-CHYI
分类号 H01L21/02;H01L21/321;(IPC1-7):H01L21/20 主分类号 H01L21/02
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