发明名称 |
Process for fabricating a aligned LDD transistor |
摘要 |
A shallow impurity diffusion layer adjacent to a gate electrode is formed by forming a side-wall insulating film of the gate electrode twice, and a MOS transistor of the salicide type having improved short-channel effect is embodied. An impurity diffusion layer portion not adjacent to a gate electrode of a source/drain region is formed first by self-alignment with a first side-wall insulating film. After an impurity diffusion layer adjacent to the gate electrode is formed by self-alignment with the gate electrode, a second side-wall insulating film is formed. Silicide films are formed on the gate electrode and source/drain region by self-alignment with the second side-wall insulating film.
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申请公布号 |
US6436776(B2) |
申请公布日期 |
2002.08.20 |
申请号 |
US20010820658 |
申请日期 |
2001.03.30 |
申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
NAKAYAMA TAKEO;HOKAZONO AKIRA |
分类号 |
H01L21/265;H01L21/336;H01L21/8238;(IPC1-7):H01L21/336 |
主分类号 |
H01L21/265 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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