A METHOD FOR A SHORT CHANNEL CMOS TRANSISTOR WITH SMALL OVERLAY CAPACITANCE USING IN-SITU DOPED SPACERS WITH A LOW DIELECTRIC CONSTANT
摘要
The method for a transistor using a replacement gate process that has a doped low-K dielectric spacer that lowers the junction capacitance. A dummy gate is formed over a substrate. Ions are implanted into the substrate using the dummy gate as an implant mask to form source and drain regions. A masking layer is formed on the substrate over the source and drain regions. We remove the dummy gate. Doped low k spacers are formed on the sidewalls of the masking layer. The doped spacers are heated to diffuse dopant into the substrate to form lightly doped drain (LDD regions). We form a high k gate dielectric layer over the masking layer. A gate layer is formed over the high K dielectric layer. The gate layer is chemical-mechanical polished (CMP) to form a gate over the high k dielectric layer and to remove the gate layer over the masking layer.
申请公布号
SG90788(A1)
申请公布日期
2002.08.20
申请号
SG20010007433
申请日期
2001.11.29
申请人
CHARTERED SEMICONDUCTOR MANUFACTURING, LTD
发明人
RANDALL CHER LIANG, CHA;TAE JONG, LEE;ALEX, SEE;LAP, CHAN;CHEE TEE, CHUA