INFORMATION PROCESSING DEVICE

摘要

PROBLEM TO BE SOLVED: To allow mode transition from the low power consumption mode to the normal operation mode without enlarging a hardware circuit for returning the whole system to the normal operation mode. SOLUTION: Even when a ROM 02, a DRAM 03 or a system bus 12 is at the low power consumption mode, a SRAM 05 accessible by a CPU 01 is provided with the system and a first mode returning processing program for returning each operation mode of the system bus 12, a ROM controller 08 and a RAM controller 09 to the normal operation mode is previously stored in the SRAM 05. When the whole system is at the low power consumption mode, the CPU 01 accesses the SRAM 05 for executing the first mode returning processing program. Thereby the CPU 01 accesses the ROM 02 or the DRAM 03 which are returned to the normal operation mode for executing a second mode returning processing program stored therein.