CLOCK GENERATING CIRCUIT AND DATA PROCESSING SYSTEM

摘要

PROBLEM TO BE SOLVED: To provide a clock generating circuit capable of controlling a frequency with a simple circuit, restricting the generation of a glitch, and generating several clock signals restricted in skew. SOLUTION: A counter 13 counts a level change when a clock signal PS0 rises, and in response to the generation of carrier at each bit by counting, carrier signals CT1-CTn having the predetermined frequency and synchronized with the level change when the clock signal PS0 rises are generated per each bit. One signal corresponding to the selecting signal SEL is selected among the predetermined signal including these generated carrier signals by a selector 14, and output as a signal C-SEL. A clock gate circuit 15 generates a signal as a clock signal BCKL obtained by thinning out a pulse of the clock signal PS0 at a time point corresponding to the level change.