| 摘要 |
PROBLEM TO BE SOLVED: To provide a viterbi detector to be implemented by a single piece of hardware, by which a sampling rate for processing a partial response maximum likelihood(PRML) signal is varied and different parameters are used. SOLUTION: The viterbi detector is provided with an input buffer (1802), a branch metric arithmetic unit (804), an addition/comparison/selection(ACR) circuit (1806), a pass memory unit (1808) and a clock buffer (1810). A viterbi is designed based on synthetic trellis chart relation which is obtained by synthesizing trellis chart relation related to a PR equalizing processing using the parameters. Thus, the viterbi detector has such a merit that hardware space is saved and the PR equalizing processing is conveniently changed through the use of the different parameters.
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