| 摘要 |
<p>PROBLEM TO BE SOLVED: To reduce a consumption current at the time when the frequency of a clock signal is low in a clock generation circuit. SOLUTION: When a clock selection circuit 30 selects a clock signal CLKA of a high frequency, the clock signal CLKA is supplied at high speed to each circuit block by enhancing the performance of a clock driver circuit 50 in accordance with comparison results of a frequency comparator 40. On the contrary, when the clock signal CLKA of a high frequency is switched to a clock signal CLKB of a low frequency, a consumption current is reduced by lowering the driving performance of the driver circuit 50 in accordance with the comparison results of the comparator 40.</p> |
