发明名称 |
LAYOUT VERIFICATION METHOD FOR A PLURALITY OF METAL AND VIA |
摘要 |
PROBLEM TO BE SOLVED: To provide a method for verifying the layout of a plurality of metals and vias capable of realizing layout verification by using simple arithmetic processing. SOLUTION: This method comprises an extraction step (S5) for extracting a pair of vertexes included in the side of a difference between resize quantity with each side of a via is enlarged for a verification value and resize quantity with which each side of the via is enlarged for a difference between the verification value and the verification minimum value, an extraction process (S7) for extracting the pair of sides to be verified by subtracting the pair of vertexes from the side, and an interval measuring process (S8) for measuring an interval between the outside edges of the pair of sides to be verified. |
申请公布号 |
JP2002230071(A) |
申请公布日期 |
2002.08.16 |
申请号 |
JP20010026933 |
申请日期 |
2001.02.02 |
申请人 |
MATSUSHITA ELECTRIC IND CO LTD |
发明人 |
HONMA JUNKO;KIMURA SHINICHI;ITO MITSUSANE |
分类号 |
H01L21/66;G06F17/50;H01L21/027;H01L21/82;(IPC1-7):G06F17/50 |
主分类号 |
H01L21/66 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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