发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT AND INSPECTING METHOD THEREOF
摘要 PROBLEM TO BE SOLVED: To perform an inspection with one test pattern in the case where flip-flop circuits to be operated with a positive phase clock and a negative phase clock exist together. SOLUTION: This semiconductor integrated circuit is provided with a selector circuit 421 for selecting any one of a clock signal and a reverse clock signal obtained by reversing the clock signal to supply it to a flip-flop circuit. When the selector circuit 421 selects the clock signal, a logic circuit 412 connected to a former stage of the flip-flop circuits 401, 403 to be operated by the positive phase clock is inspected. When the selector circuit 421 selects the reverse clock signal, a logic circuit 411 connected to a former stage of the flip-flop circuits 402 and 404 to be operated by the negative phase clock is inspected.
申请公布号 JP2002228723(A) 申请公布日期 2002.08.14
申请号 JP20010028670 申请日期 2001.02.05
申请人 ASAHI KASEI MICROSYSTEMS KK 发明人 KAMESHIMA YUJI
分类号 G01R31/28;(IPC1-7):G01R31/28 主分类号 G01R31/28
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