DYNAMIC RANDOM ACCESS MEMORY DEVICE AND FABRICATING METHOD THEREOF

摘要

PURPOSE: A method for fabricating a dynamic random access memory(DRAM) device is provided to reduce parasitic capacitance, by making the gap between storage node contact plugs filled with a silicon oxide layer of a low dielectric constant such that the storage node contact plugs pass between bitlines. CONSTITUTION: A metal oxide semiconductor(MOS) transistor is formed on a substrate(10). An interlayer dielectric is formed on the MOS transistor. A conductive layer for a bitline, a sub silicon oxide layer and a sub silicon nitride layer are stacked on the interlayer dielectric and patterned to form a bitline pattern. A bitline interlayer dielectric of a silicon oxide layer material is stacked on the bitline pattern and planarized to expose the upper surface of the sub silicon nitride layer. The sub silicon nitride layer is wet-etched to form a groove. The sub silicon oxide layer and the bitline interlayer dielectric near the groove are isotropically etched to form an enlarged groove exposing the bitline. A silicon nitride layer is stacked on the enlarged groove and anisotropically etched to expose the bitline interlayer dielectric so that a silicon nitride layer pattern is formed. A silicon nitride layer spacer is formed on the sidewall of the enlarged groove over the bitline in the bitline pattern region having an enlarged width. An interlayer dielectric for an interconnection is stacked on the entire substrate over the plate electrode and patterned to form a metal contact hole. A conductive layer is stacked to form a plug.