| 摘要 |
PURPOSE: A demodulator with a digital intermediate frequency down converter is provided to simplify a circuit thereof by utilizing a fixed clock a demodulator for demultiplexing a modulated data such as BPSK, QPSK and 16QAM and to give various data speed by incorporating therein a digital intermediate frequency down converter. CONSTITUTION: A demodulator provided with a digital intermediate frequency down converter includes an analog-to-digital(A/D) converter(31) for converting an input signal to a digital signal, a first down converter(32) for proceeding a first intermediate frequency(IF) down conversion by receiving the converted digital signal, a second down converter(33) for proceeding a second IF down conversion by inputting the first IF down converted signal, an automatic gain control(AGC) circuit(34) for supplying an I and Q data to a decoder by gain controlling the output of the second down converter(33), a symbol timing recovery circuit(35) for time recovering the gain controlled I and Q data symbol, a loop filter(36) for outputting the output from the symbol timing recovery circuit(35), a symbol numerically controlled oscillator(NCO)(37) for supplying by generating a predetermined signal at the second down converter(33), a carrier wave discriminator(38) for outputting by discriminating the carrier wave by receiving the I and Q data, a loop filter(39) for filtering the output of the carrier wave discriminator(38) and an NCO(40) for creating a predetermined signal in response to the output of the loop filter(39) and for supplying the predetermined signal to the second down converter(33).
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