| 摘要 |
A table describing the time transition relationships between flip-flops within a CRC circuit on a transmitting side is transformed, so that a table inverting the time transition relationships is generated. An inverse CRC circuit is generated based on the generated table. A CRC parity bit obtained by performing viterbi decoding is set as an initial state in respective flop-flops within the inverse CRC circuit. The portion except for the CRC parity bit of the decoded data is sequentially input and an operation is performed. When the entire decoded data is input, an initial state detecting unit determines that an error exists in reception data if the initial values set in the respective flip-flops within the CRC circuit by the transmitting side are not set in the respective flip-flops within the inverse CRC circuit.
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