| 摘要 |
A logical processing part is formed by a pass transistor logic element, and an output signal of the pass transistor logic element is applied to the gates of MOS transistors for differentially amplifying and latching the output signal in the latch stage. This latch stage is formed by master and slave latch circuits, and power supply to the master latch circuit is cut off while holding an information signal only in the slave latch circuit with the level of a power supply voltage thereto increased, reducing a leakage current in a sleep mode or a power down mode. A logic circuit correctly operating at a high speed with low current consumption under a low power supply voltage is provided.
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