| 摘要 |
A method for reducing the coupling capacitance between adjacent electrically conductive interconnect lines of an integrated circuit. An electrically conductive layer is deposited and etched to produce electrically conductive interconnect lines having negatively sloped sidewalls. An insulating layer is deposited on the electrically conductive interconnect lines using a directional deposition to create a void between and directly adjacent electrically conductive interconnect lines. The void has a substantially lower dielectric constant than the material of the insulating layer, which reduces the coupling capacitance between adjacent electrically conductive interconnect lines.
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