| 摘要 |
PURPOSE:To facilitate the manufacture without deteriorating characteristics, by relatively enlarging the slit width of a P2<+> which forms a gate layer by dispersion arrangement in a P2 layer of a P1-N1-P2-N2 four layer structure and then eliminating the P1 or N2 layer opposed to the center thereof. CONSTITUTION:A high density impurity layer P2<+> is dispersion-arranged as a buried gate in the P2 layer of P1-N1-P2-N2 four layer structure resulting in the enlargement of the width (d) of the slit S1. A part S2 is provided wherein the layer P1 located immediately under the center of the slit S1 is eliminated. The part S2 wherein the P1 layer is eliminated does not operate as a thyristor but as a transistor N1-P2-N2 in an element thickness direction. Therefore, when turn-off of the element it comes to an off-state simultaneously with the turn- off of a GTO thyristor part, and an off-characteristic is not deteriorated. Thus, the minumum gate arc current can be reduced without increasing turn-off times. |
