发明名称 LOGIC INTEGRATED CIRCUIT
摘要 PURPOSE:To improve utilization efficiency of MOST in unit cell by connecting source or drain of P, N channel MOST to form an output terminal, and subjecting connecting terminal between gates and one of remaining two terminals to form input terminals. CONSTITUTION:Unit cell of a master slice system is constituted of n channel MOSTQ2 and P channel MOSTQ1. In case, a drain terminal P3 of MOSTQ1 is grounded and A terminal P1 that connects the gates of MOSTQ1, Q2 is at a high level, if a high level is applied to a drain terminal P4 of MOSTQ, output of a high level is obtained from a commonly connected terminal P2. Thus it becomes a logic integrated circuit.
申请公布号 JPS5834629(A) 申请公布日期 1983.03.01
申请号 JP19810132504 申请日期 1981.08.24
申请人 TOKYO SHIBAURA DENKI KK 发明人 HIRABAYASHI KANJI
分类号 H03K19/0944;H03K19/0948;H03K19/173 主分类号 H03K19/0944
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