发明名称 Methods and apparatus for improving system performance with a shared cache memory
摘要 A computer system comprising a plurality of processors each having dedicated cache memories, another level of cache shared by the plurality of caches, and a main memory. The processors and the shared cache act as peers on a bus located between the processors and main memory. All data placed upon the bus by the main memory as a result of a read transaction are written into the shared cache. The shared cache does not initiate any transactions.
申请公布号 US6434672(B1) 申请公布日期 2002.08.13
申请号 US20000515727 申请日期 2000.02.29
申请人 HEWLETT-PACKARD COMPANY 发明人 GAITHER BLAINE D.
分类号 G06F12/08;(IPC1-7):G06F12/12 主分类号 G06F12/08
代理机构 代理人
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