| 摘要 |
The address holding part holds a write address supplied corresponding to a write command, as a held write address. The data holding part writes a held write data to a memory cell corresponding to the held write address when receiving the next write command. The address comparison part has a plurality of address comparators that compare a read address, with a held write address, by a plurality of bits. When the results of comparison of the address comparison part are coincident in a read operation, the held write data are outputted as read data. Since the read address and the held write address are compared by a plurality of address comparators, the scale of circuits in the address comparison part can be reduced. Moreover, the addresses can be compared at a high rate, so that the read operation can be performed at a high rate.
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